The present invention relates to a thin film transistor, and more particularly to a method for fabricating a thin film transistor of a liquid crystal display device in which an n or p-type polysilicon ohmic layer and a channeling layer of intrinsic polysilicon can be formed simultaneously by laser annealing of an amorphous silicon layer.
Active matrix liquid crystal displays(AMLCDs)are used for large screen area and high resolution application. In the AMLCD, pixels are driven independently by selectively activating thin film transistors(TFTs) associated with each pixel.
FIG. 1a is a schematic view of a conventional AMLCD structure. FIG. 1b illustrates a plan view representing a pixel. As shown in FIG. 1a, gate bus lines 23 and data bus lines 22 are connected to a gate driver circuit 30 and a data driver circuit 31, respectively. TFTs 21 are formed at the intersections of gate bus lines 23 and data bus lines 22. Gate electrodes of the TFTs 21 are connected to gate bus lines 23, and source electrodes are connected data bus lines 22, and the drains are connected to pixel electrodes 24.
When the voltage is applied to the gate electrode of one of TFTs 21 through an associated gate bus line 23, the TFT is turned on to charge an associated pixel electrode 24 with the input signal voltage from data driver circuit 31 through data bus line 22. As a result, the configuration of the liquid crystal changes to regulate the amount of light passing the pixel electrode 24.
FIGS. 2a-2e illustrate various steps of the conventional process for fabricating a staggered TFT.
First, an indium tin oxide(ITO) layer 2 is sputtered onto substrate 1 and etched to form the source/drain electrode and the data bus line, as shown in FIG. 2a. Phosphorus ions are then introduced into the substrate 1, ITO layer 2 being formed by a plasma enhanced chemical vapor deposition process at 250.degree. C. while supplying Ar gas containing 0.5% of PH.sub.3, as shown in FIG. 2b. Most of the phosphorus ions diffused into the ITO layer 2 in the depth less than 6 nm or remain on the surface of ITO layer 2.
As shown in FIG. 2c, an amorphous silicon(a-Si)is deposited on substrate 1 and ITO layer 2, and etched to form active layer 9. Accordingly, phosphorus in ITO layer 2 is diffused into semiconductor layer 9 to create a doped n.sup.+ a-Si ohmic contact region. Further, an undoped portion of semiconductor layer 9 between ITO layers 2 will become a channel layer 3 consisting of intrinsic a-Si in the a-Si TFT device.
As shown in FIGS. 2d and 2e, a gate insulating layer 5 consisting of SiNx is next formed over the entire area of the substrate 1. A metal layer is then deposited and etched to form the gate electrode 6. Lastly, a passivation layer 7 is formed over the entire area of substrate 1.
In the TFT fabricated by the above-mentioned method, however, it is difficult to maintain a sufficient amount of impurities on the surface of the ITO layer. Thus, it is difficult to form ohmic layer 4 according to the above-described method. In addition, the electron mobility in a-Si is relatively low. Thus, the switching speed of the above-described TFT is poor.